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Freescale Semiconductor /MKW21Z4 /GENFSK_REGS /IRQ_CTRL

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Interpret as IRQ_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SEQ_END_IRQ 0 (0)TX_IRQ 0 (0)RX_IRQ 0 (0)NTW_ADR_IRQ 0 (0)T1_IRQ 0 (0)T2_IRQ 0 (0)PLL_UNLOCK_IRQ 0 (0)WAKE_IRQ 0 (0)RX_WATERMARK_IRQ 0 (0)TSM_IRQ 0 (0)SEQ_END_IRQ_EN 0 (0)TX_IRQ_EN 0 (0)RX_IRQ_EN 0 (0)NTW_ADR_IRQ_EN 0 (0)T1_IRQ_EN 0 (0)T2_IRQ_EN 0 (0)PLL_UNLOCK_IRQ_EN 0 (0)WAKE_IRQ_EN 0 (0)RX_WATERMARK_IRQ_EN 0 (0)TSM_IRQ_EN 0 (0)GENERIC_FSK_IRQ_EN 0 (0)CRC_IGNORE 0 (0)CRC_VALID

GENERIC_FSK_IRQ_EN=0, CRC_VALID=0, T1_IRQ_EN=0, NTW_ADR_IRQ=0, RX_IRQ_EN=0, NTW_ADR_IRQ_EN=0, RX_WATERMARK_IRQ=0, TSM_IRQ=0, T2_IRQ_EN=0, PLL_UNLOCK_IRQ=0, T2_IRQ=0, RX_IRQ=0, TX_IRQ=0, SEQ_END_IRQ=0, T1_IRQ=0, TSM_IRQ_EN=0, SEQ_END_IRQ_EN=0, TX_IRQ_EN=0, WAKE_IRQ=0, RX_WATERMARK_IRQ_EN=0, CRC_IGNORE=0, WAKE_IRQ_EN=0, PLL_UNLOCK_IRQ_EN=0

Description

IRQ CONTROL

Fields

SEQ_END_IRQ

Sequence End Interrupt

0 (0): Sequence End Interrupt is not asserted.

1 (1): Sequence End Interrupt is asserted.
TX_IRQ

TX Interrupt

0 (0): TX Interrupt is not asserted.

1 (1): TX Interrupt is asserted.
RX_IRQ

RX Interrupt

0 (0): RX Interrupt is not asserted.

1 (1): RX Interrupt is asserted.
NTW_ADR_IRQ

Network Address Match Interrupt

0 (0): Network Address Match Interrupt is not asserted.

1 (1): Network Address Match Interrupt is asserted.
T1_IRQ

Timer1 (T1) Compare Interrupt

0 (0): Timer1 (T1) Compare Interrupt is not asserted.

1 (1): Timer1 (T1) Compare Interrupt is asserted.
T2_IRQ

Timer2 (T2) Compare Interrupt

0 (0): Timer2 (T2) Compare Interrupt is not asserted.

1 (1): Timer2 (T2) Compare Interrupt is asserted.
PLL_UNLOCK_IRQ

PLL Unlock Interrupt

0 (0): PLL Unlock Interrupt is not asserted.

1 (1): PLL Unlock Interrupt is asserted.
WAKE_IRQ

Wake Interrrupt

0 (0): Wake Interrupt is not asserted.

1 (1): Wake Interrupt is asserted.
RX_WATERMARK_IRQ

RX Watermark Interrupt

0 (0): RX Watermark Interrupt is not asserted.

1 (1): RX Watermark Interrupt is asserted.
TSM_IRQ

TSM Interrupt

0 (0): TSM0_IRQ and TSM1_IRQ are both clear.

1 (1): Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS.
SEQ_END_IRQ_EN

SEQ_END_IRQ Enable

0 (0): Sequence End Interrupt is not enabled.

1 (1): Sequence End Interrupt is enabled.
TX_IRQ_EN

TX_IRQ Enable

0 (0): TX Interrupt is not enabled.

1 (1): TX Interrupt is enabled.
RX_IRQ_EN

RX_IRQ Enable

0 (0): RX Interrupt is not enabled.

1 (1): RX Interrupt is enabled.
NTW_ADR_IRQ_EN

NTW_ADR_IRQ Enable

0 (0): Network Address Match Interrupt is not enabled.

1 (1): Network Address Match Interrupt is enabled.
T1_IRQ_EN

T1_IRQ Enable

0 (0): Timer1 (T1) Compare Interrupt is not enabled.

1 (1): Timer1 (T1) Compare Interrupt is enabled.
T2_IRQ_EN

T2_IRQ Enable

0 (0): Timer1 (T2) Compare Interrupt is not enabled.

1 (1): Timer1 (T2) Compare Interrupt is enabled.
PLL_UNLOCK_IRQ_EN

PLL_UNLOCK_IRQ Enable

0 (0): PLL Unlock Interrupt is not enabled.

1 (1): PLL Unlock Interrupt is enabled.
WAKE_IRQ_EN

WAKE_IRQ Enable

0 (0): Wake Interrupt is not enabled.

1 (1): Wake Interrupt is enabled.
RX_WATERMARK_IRQ_EN

RX_WATERMARK_IRQ Enable

0 (0): RX Watermark Interrupt is not enabled.

1 (1): RX Watermark Interrupt is enabled.
TSM_IRQ_EN

TSM_IRQ Enable

0 (0): TSM Interrupt is not enabled.

1 (1): TSM Interrupt is enabled.
GENERIC_FSK_IRQ_EN

GENERIC_FSK_IRQ Master Enable

0 (0): All GENERIC_FSK Interrupts are disabled.

1 (1): All GENERIC_FSK Interrupts can be enabled.
CRC_IGNORE

CRC Ignore

0 (0): RX_IRQ will not be asserted for a received packet which fails CRC verification.

1 (1): RX_IRQ will be asserted even for a received packet which fails CRC verification.
CRC_VALID

CRC Valid

0 (0): CRC of RX packet is not valid.

1 (1): CRC of RX packet is valid.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data